Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit
US4989140A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 13, 1989 |
| Grant date | Jan 29, 1991 |
| Priority date | — |
| Expiry date | Mar 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instruction read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output the instruction to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.