Pipelined address check bit stack controller
US4989210A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1990 |
| Grant date | Jan 29, 1991 |
| Priority date | — |
| Expiry date | Mar 19, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1056
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system which is shared by a plurality of requestors each of which supply read and write address bits to the memory system is read out of, or written into, in accordance with read and write address bits. A sequencer is utilized to initiate a sequence of timing signals that control the reading, writing and partial writing of data. Certain ones of these signals occur at fixed intervals from the receipt of an initial load address signal. A read address circuit coupled to receive the read address bits generates a set of check bits. A read address stack means stores each set of read address check bits upon the occurrence of an associated load read address stack signal. A write address check bit generator means is coupled to receive write address bits and to generate a set of check bits representative of the write address bits. A write address stack means stores each set of the write address check bits upon the occurrence of an associated load write address stack signal. A read address stack selector and a write address stack selector read out read address check bits and write address check bits, while the sequencer controls the transmission of the read address check bits and the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.