High voltage merged bipolar/CMOS technology

US4994887A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Louis N. Hutter · Richardson, US
• Mark Edward Gibson · Mesquite, US
• Jeffrey P. Smith · San Diego, US
• Shiu-Hang Yan · Richardson, US
• Arnold C. Conway · Garland, US
• John P. Erdeljac · Plano, US
• James D. Goon · Dallas, US
• Anhkim Duong · Garland, US
• Mary Ann Murphy · Richardson, US
• Susan S. Kearney · Tully, US

Key dates

• Filing date: Nov 13, 1987
• Grant date: Feb 19, 1991
• Expiry date: Nov 13, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/401

Abstract

An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.