Coprocessor instruction format
US4994961A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1987 |
| Grant date | Feb 19, 1991 |
| Priority date | — |
| Expiry date | Sep 18, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.