Manufacturing process for an integrated circuit comprising double gate components

US4997777A · kind A · utility

Inventor

• Philippe Boivin · Venelles, FR

Key dates

• Filing date: Dec 14, 1988
• Grant date: Mar 5, 1991
• Expiry date: Dec 14, 2008

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A process for manufacturing integrated circuits comprising insulated gate MOS transistors and double gate memory components, comprises the following steps: forming on the areas where the memory components will be formed a first insulating layer (2) and a first gate level (4); forming on the transistor areas and the memory areas a second insulating layer (5), a second gate level (6) and a first photoresist layer (7); etching the first photoresist layer and the second gate level according to chosen configurations; coating the transistor areas with a second photoresist layer (20). This process further comprises the following steps: selectively etching the second photoresist layer at the center of the places where the transistor drains and sources are to be formed; etching the apparent oxide areas and then the apparent gate and substrate areas; removing the second photoresist layer; and carrying out an ionic implantation of the drains and sources.