Floating point arithmetic two cycle data flow
US4999802A · kind A · utility
21Cited by
22References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 1989 |
| Grant date | Mar 12, 1991 |
| Priority date | — |
| Expiry date | Jan 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49947
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.