Stephen L. Runyon
19Patents
9h-index
36Co-inventors
72Inventor score
Filing activity: Jan 13, 1989 → May 5, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5212662A | Floating point arithmetic two cycle data flow | Physics | 23 | Expired |
| US4999802A | Floating point arithmetic two cycle data flow | Physics | 21 | Expired |
| US5646557A | Data processing system and method for improving performance of domino-type logic using multiphase clocks | Electricity | 20 | Expired |
| US6507930B1 | Method and system for improving yield of semiconductor integrated circuits | Electricity | 16 | Expired |
| US7627836B2 | OPC trimming for performance | Physics | 11 | Expired |
| US7759173B2 | Methods for charge dissipation in integrated circuits | Electricity | 10 | Active |
| US7363601B2 | Integrated circuit selective scaling | Physics | 10 | Expired |
| US6320237A | Decoupling capacitor structure | Electricity | 9 | Expired |
| US6480992B1 | Method, apparatus, and program product for laying out capacitors in an integrated circuit | Physics | 9 | Expired |
| US7882463B2 | Integrated circuit selective scaling | Physics | 7 | Active |
| US6571374B1 | Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips | Physics | 5 | Expired |
| US6777304B2 | Method for producing an integrated circuit capacitor | Electricity | 4 | Expired |
| US7568173B2 | Independent migration of hierarchical designs with methods of finding and fixing opens during migration | Physics | 3 | Active |
| US6406980B1 | Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets | Electricity | 3 | Expired |
| US7378318B2 | System and method for ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits | Electricity | 2 | Expired |
| US7408206B2 | Method and structure for charge dissipation in integrated circuits | Electricity | 2 | Active |
| US7865848B2 | Layout optimization using parameterized cells | Physics | 2 | Active |
| US6567958B1 | Invention to allow hierarchical logical-to-physical checking on chips | Physics | 1 | Expired |
| US7537997B2 | Ensuring migratability of circuits by masking portions of the circuits while improving performance of other portions of the circuits | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.