Trench DRAM cell with dynamic gain
US4999811A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1987 |
| Grant date | Mar 12, 1991 |
| Priority date | — |
| Expiry date | Nov 30, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two transistor gain-type dynamic random access memory (DRAM) cell (8) formed in a trench (30) to optimize wafer area requirements. Formed on a heavily doped semiconductor substrate (20) are alternate layers of P-type and N-type semiconductor material defining the elements of a vertical pass transistor (12) and gain transistor (24). A trench is formed through the alternate semiconductor layers into the substrate (20), and filled with two regions of a semiconductor material defining a storage node (18) and, insulated therefrom, a word line (16). The gain transistor (24) is fabricated having a response time faster than that of the pass transistor (12) so that, during read operations, the gain transistor (24) changes the precharged voltage of the read bit line (26), depending upon the charge stored in the capacitor storage node (18).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.