Method of fabricating a high performance interconnect system for an integrated circuit
US5000818A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 1990 |
| Grant date | Mar 19, 1991 |
| Priority date | — |
| Expiry date | May 18, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.