High speed complementary field effect transistor logic circuits
US5001367A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 1989 |
| Grant date | Mar 19, 1991 |
| Priority date | — |
| Expiry date | Apr 14, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09485
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed, high density, low power dissipation all parallel FET logic circuit includes a driving stage having a plurality of parallel FETs of a first conductivity type for receiving logic input signals and a load FET of second conductivity type connected to the common output of the driving stage. A complementary FET inverter including serially connected FETs of first and second conductivity type is connected to the common output and the load FET. According to the invention the voltage transfer function of the complementary inverter is skewed so that the product of the carrier mobility and the ratio of channel width to length of the inverter FET of the first conductivity type is made substantially greater than the product of the carrier mobility and the ratio of channel width to length of the inverter FET of the second conductivity type. By skewing the voltage transfer function of the complementary inverter the voltage lift-off interval is dramatically decreased, thereby improving the speed. AND and OR circuits and combined AND-OR circuits may be provided, having true and complement outputs. A multigate serial load transistor may further reduce power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.