Event qualified testing architecture for integrated circuits
US5001713A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 8, 1989 |
| Grant date | Mar 19, 1991 |
| Priority date | — |
| Expiry date | Feb 8, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/86
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A boundary test architecture for use in an integrated circuit (10) comprises input and output test registers (12, 22) having functions controlled by an event qualifying module (EQM) (30). The EQM (30) receives a signal from the output test register (22) indicating that a matching condition has been met. In response to a matching condition, EQM (30) may control the input and output test registers (12, 22) to perform a variety of tests on the incoming and outgoing data. During testing, the internal logic (20) may continue to operate at-speed, thereby allowing the test circuitry to detect faults which would not otherwise be discoverable. A memory buffer (64) may be included to store a plurality of input data for test data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.