Integrated-circuit device isolation
US5002898A · kind A · utility
12Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1989 |
| Grant date | Mar 26, 1991 |
| Priority date | — |
| Expiry date | Oct 19, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76202
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the manufacture of integrated-circuit semiconductor devices, prior to formation of a field oxide, a mask structure is provided on a silicon device area, comprising a pad oxide layer, a polysilicon buffer layer, a protective oxide layer, and a silicon nitride mask layer. Inclusion of the protective layer between polysilicon and silicon nitride layers prevents pad oxide failure and attendant substrate etching during strip-etching of the structure overlying the pad oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.