Semiconductor memory device having error correcting circuit and method for correcting error
US5003542A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1988 |
| Grant date | Mar 26, 1991 |
| Priority date | — |
| Expiry date | Nov 15, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device having an error correcting circuit, a pair of bit lines and inverted bit lines are connected to the inputs of first and second inverting amplitude circuits through a first and second N channel MOS transistors, respectively, and the output of the first inverting amplitude circuit is connected to the bit line through a third transistor and the output of the second inverting amplitude circuit is connected to the inverted bit line through a fourth transistor. When an error of information of any bit line pair is detected by an error detecting circuit, the first and second N channel MOS transistors are turned off and each bit line pair is separated from the input of the first and second inverting amplitude circuits and, as a result, information of a bit line pair is rewritten by the output of the first and second inverting amplitude circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.