Inverted epitaxial process
US5004705A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 1989 |
| Grant date | Apr 2, 1991 |
| Priority date | — |
| Expiry date | Jan 6, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/012
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a semiconductor device by forming a diffusion region in a first semiconductor wafer and bonding the surface of the first semiconductor wafer having the diffused region to a second semiconductor wafer to form a low resistance buried layer. The process includes further diffusion to provide an external electrical contact with the buried layer. Further enhancements are provided by selectively forming voids and/or selectively applying materials of greater and lesser conductivity on at least one of the semiconductor wafers before bonding, forming complex internal semiconductor structures in the bonded wafer structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.