Dual zone, fault tolerant computer system with error checking in I/O writes
US5005174A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1990 |
| Grant date | Apr 2, 1991 |
| Priority date | — |
| Expiry date | Feb 26, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant computer system having a first processing system which includes a first data processor for executing a series of data processing instructions. A first data output terminal outputs data from the first processing system. A second processing system, substantially identical to the first processing system, operates independently from the first processing system. The second processing system includes a second data processor for executing the series of data processing instructions in the same sequence as the first data processor. It also includes a second data output terminal for outputting data from the second processing system. A synchronizing device is coupled to the first and second data processors for maintaining the execution of the series of data processing instructions by the first and second processing systems in synchronism. Fault detection devices are coupled to the first and second data output terminals for comparing the data output from the first processing system with the data output from the second processing system. The fault detection devices identify the presence of an error when the data output from the first processing system at the first output termin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.