Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices
US5006477A · kind A · utility
37Cited by
5References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 25, 1988 |
| Grant date | Apr 9, 1991 |
| Priority date | — |
| Expiry date | Nov 25, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/053
Abstract
A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.