Method of fabricating a narrow base transistor
US5008207A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1989 |
| Grant date | Apr 16, 1991 |
| Priority date | — |
| Expiry date | Sep 11, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/969
Abstract
There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.