Selective asperity definition technique suitable for use in fabricating floating-gate transistor
US5008212A · kind A · utility
Inventor
Key dates
| Filing date | Dec 12, 1988 |
| Grant date | Apr 16, 1991 |
| Priority date | — |
| Expiry date | Dec 12, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor fabrication technique, a first patterned layer (16) of nonmonocrystalline semiconductor material is created on a substructure (10, 12, 14). An insulating layer (22) is thermally grown along the patterned layer in such a way that the upper edge of the remainder (16A) of the patterned layer forms an asperity (24). A blanket layer 26, preferably consisting of nonmonocrystalline semiconductor material, is formed over the insulating layer. Using an etchant that attacks the blanket and patterned layers more than the insulating layer, a selective etch is performed to remove a section of the blanket layer. The etch is continued past the blanket layer to remove the underlying portion of the insulating layer located along the asperity and then, importantly, to remove the so exposed part of the asperity. The remainder (26A) of the blanket overlies the remainder ( (24A) of the asperity. The technique is particularly useful in manufacturing a floating-gate FET for an electrically erasable programmable device. The remainder of the asperity facilitates tunneling during erasure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.