Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects
US5010032A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1989 |
| Grant date | Apr 23, 1991 |
| Priority date | — |
| Expiry date | Oct 5, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.