Semiconductor memory device
US5010518A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 1989 |
| Grant date | Apr 23, 1991 |
| Priority date | — |
| Expiry date | Oct 16, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a first bit line, a second bit line paired with the first bit line, a third bit line branch-connected with the first bit line, a fourth bit line paired with the third bit line and branch-connected with the second bit line, a memory cell array connected to the bit lines, a first reference cell, and a second reference cell. The first reference cell is connected to the first bit line and the third bit line, constituted by a cell which is formed of substantially the same area, capacity and structure as the memory cell array, and providing a reference potential at the time of reading out data from memory cells in the memory cell array. And the second reference cell is connected to the second bit line and the fourth bit line, constituted by a cell which is formed of substantially the same area, capacity and structure as the memory cell array, and providing a reference potential at the time of reading out data from the memory cells in the memory cell array. The memory cell array is a non-volatile type constituted by ferroelectric cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.