Crosstalk-shielded-bit-line dram
US5010524A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1989 |
| Grant date | Apr 23, 1991 |
| Priority date | — |
| Expiry date | Apr 20, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit or column lines are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines associated with a common sense amplifier. One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.