Dynamic type semiconductor memory device having an error checking and correcting circuit
US5012472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1988 |
| Grant date | Apr 30, 1991 |
| Priority date | — |
| Expiry date | Dec 22, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory cell comprising a data cell array and a parity cell array, an error checking.multidot.correcting circuit is connected to each of the arrays through a selector. The selector is constituted by transistors connected to each of the bit lines in the memory cell. The number of circuit elements constituting the error checking.multidot.correcting circuit corresponds to one-half of the number of the bit line pairs included in the data cell array and the parity cell array. In an error correcting mode, half of the data appeared on the bit line pairs in data cell array and the parity cell array are transferred to the error checking.multidot.correcting circuit by the selector, so that the errors are corrected. Thereafter, the data of the remaining half of the bit line pairs are processed in the same manner. Therefore, the number of circuit elements of the error checking.multidot.correcting circuit can be reduced compared with the prior art, improving the degree of integration of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.