Quad processor
US5013385A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1989 |
| Grant date | May 7, 1991 |
| Priority date | — |
| Expiry date | Dec 1, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/141
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafers are movable within the controlled environment one at a time selectably between the several plasma vessels and the wafer queuing station without atmospheric or other exposure to that possible contamination of the moved wafers is prevented. The system is selectively operative in either single-step or multiple-step processing modes, and in either of the modes, the several plasma etching vessels are operable to provide a desirably high system throughput. In the preferred embodiment, the several plasma vessels and the queuing station are arrayed about a closed pentagonal locus with the wafer transfer arm disposed within the closed locus. Wafer processing in each vessel is regulated by a state controller for processing a plurality of wafers from a single cassette, contained within the vacuum environment of the plural plasma etching vessels and wafer queuing station, to provide an orderly and efficient throughput of wafers for diverse or similar processing in the plural vessels. In this manner a wafer can be processed as soon as a v…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.