Method of forming and removing polysilicon lightly doped drain spacers

US5013675A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Lewis Shen · Cupertino, US
• Zahra Hadjizadeh-Amini · Cupertino, US
• Hsingya Arthur Wang · Saratoga, US
• James Hsu · Cincinnati, US

Key dates

• Filing date: May 23, 1989
• Grant date: May 7, 1991
• Expiry date: May 23, 2009

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/601

Abstract

A method of forming and removing spacers used to mask lightly doped drain (LDD) regions in the formation of a field effect transistor (FET) involves depositing a thin oxide layer over the active region of a substrate and a gate structure formed on the active region. A polysilicon film is provided over the oxide and then doped using a POCl.sub.3 dopant. The polysilicon layer is then etched to form spacers at the ends of the gate and the spacers are used to mask lightly doped drain regions in the substrate during the implantation of source and drain regions. After the implant to form the source and drain regions, the device is subjected to a rapid thermal annealing for approximately 20-60 seconds at approximately 900.degree. C. in an inert atmosphere to cure any damage to the oxide layer which occurs during the source/drain implant. Curing the oxide layer reduces the etch rate of the oxide layer for an etchant which is designed to selectively etch the polysilicon spacers faster than it etches the oxide layer. The POCl.sub.3 doping of the polysilicon layer increases the etch rate of the polysilicon, thus enhancing the selectivity of the etching of the polysilicon versus the oxide laye…