Programmable delay line utilizing measured actual delays to provide a highly accurate delay
US5013944A · kind A · utility
20Cited by
14References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1989 |
| Grant date | May 7, 1991 |
| Priority date | — |
| Expiry date | Apr 20, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00254
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of operating a delay circuit to impose a selected delay on an electronic signal the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method comprising the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.