Multiple array high performance programmable logic device family
US5015884A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1990 |
| Grant date | May 14, 1991 |
| Priority date | — |
| Expiry date | Mar 7, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O marcrocells decouple the logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.