Amorphous silicon thin film transistor array
US5017984A · kind A · utility
25Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1990 |
| Grant date | May 21, 1991 |
| Priority date | — |
| Expiry date | Jun 4, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2202/103
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An amorphous silicon thin film transistor array substrate has a gate insulating layer and an amorphous silicon layer formed on gate wiring. A pattern of a protective insulating layer having a stepped edge is formed on the amorphous silicon layer. An upper electrode of the same material as the source electrode and the drain electrode are formed on the protective insulating layer to cover the stepped edge of the protective insulating layer. A hold capacitance is formed by connecting the upper electrode to a pixel electrode on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.