Static random access memory with modulated loads
US5018106A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1989 |
| Grant date | May 21, 1991 |
| Priority date | — |
| Expiry date | Apr 27, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) comprises plural memory cells, a true-bit load and a complementary-bit load, a true-bit line and a complementary bit line, a sense amplifier and an address transition detector. The address transition detector is used to generate load pulses which switch off the loads just after either of the memory cells is selected. This speeds signal development during a read (or write) operation. Since provision is made for modulating the loads, they can be designed to permit larger-than-conventional currents to flow therethrough when maximally on. The loads are maximally on just after cell deselection to facilitate bit-line equalization between cell selections. Thus, the present invention provides for briefer inter-select periods, quicker reads upon cell selection, and, thus, a faster SRAM overall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.