Method for forming a horizontal self-aligned transistor
US5019525A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1990 |
| Grant date | May 28, 1991 |
| Priority date | — |
| Expiry date | Jul 5, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/15
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a self-aligned horizontal transistor includes the step of first defining a narrow base contact on an isolated N-tank (10) to define a first reference edge (41). A layer of sidewall oxide (40) is then disposed on the vertical wall of the base contact (34) to define a second reference edge (42). An emitter well (44) and a collector well (46) are then defined on either side of the contact with the vertical wall of the emitter well (44) aligned with the reference edge (42). A dopant material is then disposed adjacent the reference edge (42) and the dopant diffused into the substrate from a lateral direction to form a P-type base region (58) with a graded impurity profile. N-doped regions (64) and (66) are then formed in the emitter and collector wells to form the emitter and collector of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.