Method of manufacturing non-volatile semiconductor memories, in which selective removal of field oxidation film for forming source region and self-adjusted treatment for forming contact portion are simultaneously performed
US5019527A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1990 |
| Grant date | May 28, 1991 |
| Priority date | — |
| Expiry date | Aug 9, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is formed on a surface of a first conductivity type semiconductor substrate strip shaped first insulator separately extending in parallel with one another. A plurality of stacked gate structures, each comprising a second insulator, a floating gate, a third insulator, a control gate, a fourth insulator and an etching stopper having a slower etching speed than the fourth insulator, are formed on the substrate and the first insulator. Those portions of each first insulator that are located between the parallel extending gate structures and are present at prospective source regions are self-aligningly removed with using one end side of each gate structure as a part of a mask, so as to expose those portions of the substrate that are located at the prospective source regions. Impurities of a second conductivity type are self-aligningly introduced into each prospective source region with using one end side of each gate structure as a part of a mask to form a fifth insulator on a side wall of each gate structure. Impurities of the second conductivity type are self-aligningly introduced into each of prospective drain regions with using a drain side end of each gate structure as a part…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.