Process for RIE etching silicon dioxide
US5021121A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1990 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Feb 16, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldMaterials, metallurgy
- WIPO sectorChemistry
Abstract
An improved RIE process is disclosed for etching one or more openings in a layer of an oxide of silicon on a semiconductor wafer characterized by a contact angle of at least 80.degree., with respect to the plane of the oxide layer, and highly selective to silicon which comprises flowing an inert gas and CHF.sub.3 into an RIE chamber while maintaining respective gas flows within a range of from about 15 to about 185 sccm of inert gas and from about 15 to about 60 sccm of CHF.sub.3, with a total gas flow not exceeding about 200 sccm, and a ratio of inert gas to CHF.sub.3 ranging from about 1:1 to about 10:1. A plasma is maintained in the RIE chamber during the gas flow at a power level within a range of from about 400 to about 1000 watts. In a preferred embodiment, CF.sub.4 gas is also flowed into the RIE chamber within a range of from about 1 to about 10 sccm to control the selectivity of the etch to silicon, and the wafer is immersed in a magnetic field of 1 to 120 gauss during the etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.