Compound semiconductor interface control using cationic ingredient oxide to prevent fermi level pinning
US5021365A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1989 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Mar 13, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/118
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Control of the Fermi level pinning problem and the production of flat band surface performance in compound semiconductors is achieved by providing a cationic oxide free of anionic species on the surface of the semiconductor for flat band performance and with a localized inclusion of some anionic species for barrier performance so that oxide and metal work function responsiveness is available in structure and performance in MOSFET, MESFET and different work function metal FET structures. A cationic gallium oxide is produced on GaAs by oxide growth during illumination and while being rinsed with oxygenated water. The oxidation is used to produce both anionic and cationic species while the rinsing process selectively removes all the anionic species.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.