Semiconductor memory having redundancy circuit for relieving defects
US5021944A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1989 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Jul 6, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for quickly masking defective memory elements with substitute memory elements includes first and second memory blocks. The first memory block includes a first memory array and a second spare memory array. The second memory block includes a second memory array and a first spare memory array. A first word from the first memory array is selected concurrently with a first substitute word from the first spare memory. An address signal is decoded and then compared with data representative of a defective word. In the event it is determined, as a result of this comparison, that the first word is defective, the first substitute word is then communicated to a common data bus. Alternatively, the first word is communicated to the common data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.