Variable latency method and apparatus for floating-point coprocessor
US5021985A · kind A · utility
45Cited by
2References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1990 |
| Grant date | Jun 4, 1991 |
| Priority date | — |
| Expiry date | Jan 19, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3871
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable latency (a programmable number of clock cycles) needed for an operation completion. The required latency for a pipe is determined from a formula including the system clock cycle time which the unit will be specified to operate under. The latency is preprogrammed by setting the count of a timer accordingly to provide at least the minimum number of clock cycles necessary to cover the time required to do the computation. Separate timers are independently set for arithmetic logic unit (ALU) operations, multiply operations, logical operations and divide and square root operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.