Method of thermal balancing RF power transistor array
US5023189A · kind A · utility
21Cited by
4References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 4, 1990 |
| Grant date | Jun 11, 1991 |
| Priority date | — |
| Expiry date | May 4, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49004
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Thermal balance in an array of RF transistor cells in which all transistors are connected in parallel is obtained by interconnecting the transistors to array contacts by means of discrete wire leads. The array is electrically tested and a temperature distribution in the array is obtained. Thereafter, the wire leads are varied in length and height above the plane of the array to improve temperature distribution during test. The steps are repeated as necessary to obtain a desired temperature balance in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.