Manufacturing high speed low leakage radiation hardened CMOS/SOI devices
US5024965A · kind A · utility
Inventors
Key dates
| Filing date | Feb 16, 1990 |
| Grant date | Jun 18, 1991 |
| Priority date | — |
| Expiry date | Feb 16, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/15
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating high speed, low leakage, radiation hardened integrated circuit semiconductor devices. In accordance with the method a SIMOX (separation by ion implantation of oxygen) wafer is masked with a separation mask to form silicon islands. The separation mask forms groups of N-channel and P-channel devices that are isolated from each other. The N- and P-channel device separation assists in preventing device latch-up. N- and N-channel devices are isolated by controlling the process due to high field inversion thresholds and radiation hardened field oxide to eliminate any channel-to-channel leakage current after high dosage irradiation. A relatively thin gate oxide layer is formed over the islands, and the island edges are covered with phosphoroborosilicate glass deposited at a relatively low temperature (850.degree. C.) to eliminate sharp island edges and hence edge leakage. The use of SIMOX substrate materials, phosphoroborosilicate glass and thin oxide provides the benefits of improved speed and reduced leakage due to intrinsic oxide isolation, shallow wells and source and drain junctions. The use of a thin thermal oxide layer and phosphoroborosilicate glass elimina…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.