Assembly of semiconductor chips
US5025306A · kind A · utility
131Cited by
28References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1988 |
| Grant date | Jun 18, 1991 |
| Priority date | — |
| Expiry date | Aug 9, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three dimensional package having at least one semiconductor chip having input/output conductive pads along its periphery includes a dielectric carrier over at least a portion of the chip and a plurality of conductors mounted on the carrier between the chip and the dielectric carrier. The plurality of conductors are mounted within the periphery of the chip with one end connected to the conductive pads and with the other end of the plurality of conductors exiting from the same side of the chip. The plurality of conductors exiting from the same side are electrically coupled to an interconnect substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.