MOS transistor with improved radiation hardness
US5026656A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1990 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | Mar 2, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/953
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.