Process for fabricating stacked trench capacitors of dynamic ram
US5026659A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1990 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | Jun 7, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/047
Abstract
A process for fabricating a stacked trench capacitor of a DRAM by way of the anisotropic dry etch technique of CVD silicon. In the process, sidewalls are formed by the anisotropic dry etch of CVD silicon which is formed within a trench for good electrical isolation between trenches, and upon the wet etch of an oxide film, are served as blocking layers to leave an oxide film layer for isolation in the side surfaces of the trenches. In the bottom part of the trenches in which the oxide film is removed, the ion implantation is performed with dopants having an opposite type in relation to the impurity diffusion area of a transistor for isolating the whole of the trenches effectively. Also, on the slant trench in which sharp edges do not exist the thin dielectric layer is formed to eliminate electrical weakspots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.