Processor controlled interface with instruction streaming
US5027270A · kind A · utility
53Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1988 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | Oct 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.