Earl A. Killian
34Patents
23h-index
36Co-inventors
85Inventor score
Filing activity: Sep 27, 1983 → Jun 8, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6477683B1 | Automated processor generation system for designing a configurable processor and method for the same | Physics | 281 | Expired |
| US5933650A | Alignment and ordering of vector elements for single instruction multiple data processing | Physics | 204 | Expired |
| US7020854B2 | Automated processor generation system for designing a configurable processor and method for the same | Physics | 117 | Expired |
| US5864703A | Method for providing extended precision in SIMD vector arithmetic operations | Physics | 116 | Expired |
| US6266758A | Alignment and ordering of vector elements for single instruction multiple data processing | Physics | 100 | Expired |
| US7219212B1 | Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion | Physics | 84 | Expired |
| US6760888B2 | Automated processor generation system for designing a configurable processor and method for the same | Physics | 81 | Expired |
| US7036106B1 | Automated processor generation system for designing a configurable processor and method for the same | Physics | 69 | Expired |
| US5398328A | System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders | Physics | 57 | Expired |
| US6282633A | High data density RISC processor | Physics | 56 | Expired |
| US6477697B1 | ADDING COMPLEX INSTRUCTION EXTENSIONS DEFINED IN A STANDARDIZED LANGUAGE TO A MICROPROCESSOR DESIGN TO PRODUCE A CONFIGURABLE DEFINITION OF A TARGET INSTRUCTION SET, AND HDL DESCRIPTION OF CIRCUITRY NECESSARY TO IMPLEMENT THE INSTRUCTION SET, AND DEVELOPMENT AND VERIFICATION TOOLS FOR THE INSTRUCTION SET | Physics | 55 | Expired |
| US5027270A | Processor controlled interface with instruction streaming | Physics | 53 | Expired |
| US6854046B1 | Configurable memory management unit | Physics | 51 | Expired |
| US8006204B2 | Automated processor generation system for designing a configurable processor and method for the same | Physics | 50 | Expired |
| US5420992A | Backward-compatible computer architecture with extended word size and address space | Physics | 48 | Expired |
| US7376812B1 | Vector co-processor for configurable and extensible processor architecture | Physics | 44 | Expired |
| US5568630A | Backward-compatible computer architecture with extended word size and address space | Physics | 42 | Expired |
| US5574877A | TLB with two physical pages per virtual tag | Physics | 36 | Expired |
| US5696958A | Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline | Physics | 34 | Expired |
| US6092187A | Instruction prediction based on filtering | Physics | 34 | Expired |
| US7197625B1 | Alignment and ordering of vector elements for single instruction multiple data processing | Physics | 33 | Expired |
| US5572713A | System and method for obtaining correct byte addresses by using logical operations on 2 least significant bits of byte address to facilitate compatibility between computer architectures having different memory orders | Physics | 29 | Expired |
| US5479630A | Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same | Physics | 26 | Expired |
| US8074058B2 | Providing extended precision in SIMD vector arithmetic operations | Physics | 22 | Active |
| US8161432B2 | Automated processor generation system and method for designing a configurable processor | Physics | 12 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.