Carry-select adder
US5027312A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1989 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | Jul 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3876
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A carry-select adder composed of blocks, each containing an input adder cell and a number of adder cells of a first and second type. Each block has one input adder cell interconnected to adder cells of the first and second type which are connected in an alternating fashion. The cells are connected to each other via carry lines and block carry lines. The adder cells of the first and second type each have a gate arrangement which utilizes field effect transistors for transfer, pull-up and pull-down transistors. These transistors are not a component part of a combination gate within an adder cell. The gate arrangement significantly increases the processing speed of the carry-select adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.