Edge doping processes for mesa structures in SOS and SOI devices
US5028564A · kind A · utility
Inventors
Key dates
| Filing date | Apr 27, 1989 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Apr 27, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating heavily doped edges of mesa structures in silicon-on-sapphire and silicon-on-insulator semiconductor devices. The methods are self-aligning and require a minimum of masking steps to achieve. The disclosed methods reduce edge leakage and resolve N-channel threshold voltage instability problems. Mesa structures are formed that comprise N-channel and P-channel regions having a thermal oxide layer deposited thereover. A doping layer of borosilicate glass, or alternatively, an undoped oxide layer that is subsequently implanted, is deposited over the mesa structures. In the first method, the doping layer is etched by means of an anisotropic plasma etching procedure to form oxide spacers at the edges of the mesa structures. The doping layer is removed from the N-mesa structures using an N-channel mask and wet oxide etching procedure. The structure is then heated to a relatively high temperature to drive the dopant into the edges of the N-channel mesa structures. The protective layers are then removed by a wet etching procedure. The semiconductor device is fabricated to completion in a conventional manner thereafter. In the second method, a nitride layer is deposited…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.