Four quadrant synapse cell employing single column summing line
US5028810A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 1990 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | May 18, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention covers a synapse cell for providing a weighted connection between a differential input voltage and a single output summing line having an associated capacitance. The connection is made using one or more floating-gate transistors which provide both excitatory as well as inhibitory connections. As configured, each transistor's drain is coupled to an input line and its source is coupled to the output summing line. The floating-gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a voltage pulse having a certain duration is applied to the control gate of the floating-gate transistor, a current is generated which acts to discharge the capacitance associated with the output summing line. The current is directly proportional to the charge stored on the floating-gate member and the duration of the input pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.