Semiconductor memory device with ferroelectric capacitor cells with a plate to which a mid-level voltage is applied
US5029128A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 1989 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Sep 25, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes bit line pairs including first and second bit lines to be selectively set at a first logic level or a second logic level, and a first memory cell coupled with the first bit line of the bit line pairs. The first memory cell contains a first ferroelectric capacitor with first and second electrode plates, and a first transistor coupled between the first electrode plate of the first ferroelectric capacitor and the first bit line. A potential at the second electrode plate of the first ferroelectric capacitor is set at a mid value between the first and second logic levels. A distance D (cm) between the first and second electrode plates of the first ferroelectric capacitor being selected such that a minimum voltage Et.times.D to saturate the intensity of polarization of the first ferroelectric capacitor is smaller than the value amounting to substantially half of the difference between the first and second logic levels, where Et indicates a field strength sufficient to saturate the intensity of the polarization of the first ferroelectric capacitor and is expressed in V/cm (volts/centimeter).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.