Wordline drive inhibit circuit implementing worldline redundancy without an access time penalty
US5031151A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1990 |
| Grant date | Jul 9, 1991 |
| Priority date | — |
| Expiry date | Oct 22, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available to each of a plurality of sub-arrays of normal memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.