Semiconductor integrated circuit with dummy patterns
US5032890A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1989 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | Jan 30, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device including a semiconductor substrate, a lower interconnection layer pattern formed along first parallel lines on the substrate, an insulating layer formed on the pattern, and an upper interconnection layer pattern formed along second parallel lines perpendicularly intersecting with the first parallel lines on the insulating layer. A dummy pattern made of the same material as that of the lower interconnection layer pattern, and not electrically connected to the upper and lower interconnection layer patterns, is formed in a region which is arranged below the upper interconnection layer pattern and in which the first parallel lines intersect the second parallel lines. The dummy pattern has the same level as that of the lower interconnection layer pattern, has no lower interconnection layer pattern, and is adjacent to the lower interconnection layer pattern, at a predetermined interval from the lower interconnection layer pattern. By arranging such a dummy pattern, the insulating layer formed on the lower interconnection layer is flattened, thereby preventing disconnection of the upper interconnection layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.