High density EEPROM cell and process for making the cell
US5033023A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1988 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | Apr 8, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/711
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a stacked gate electrically erasable programmable read only memory EEPROM cell which utilizes a floating region and a common pass transistor to provide a cell which is programmable at a relatively low drain voltage and which, in addition, by utilizing a pass transistor, overcomes the programming disturbance and false read problems associated with typical stacked gate memory cells. The cell is constructed such that programming and erasing functions take place at separate locations in the gate oxide. An EEPROM memory cell array, utilizing the above memory cell, is disclosed which provides the ability to achieve both byte erase and block erase as well as byte write capability. Also disclosed is a process for producing such a memory cell and memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.