Amorphous silicon thin film transistor array substrate and method for producing the same
US5034340A · kind A · utility
22Cited by
17References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1989 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | Jun 26, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/443
Abstract
An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, a gate wiring interconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.