Planar vertical channel DMOS structure
US5034785A · kind A · utility
128Cited by
12References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1988 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | Aug 24, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A DMOS power transistor has a vertical gate and a planar top surface. A vertical gate fills a rectangular groove lined with a dielectric material which extends downward so that source and body regions lie on each side of the dielectric groove. Carriers flow vertically between source and body regions and the structure has a flat surface for all masking steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.